The present invention relates to a clock generation circuit that uses a phase locked loop (PLL) to generate multi-phase clock signals, as well as a serial/parallel conversion device, a parallel/serial conversion device, and a semiconductor device.
In general, it can happen that a data signal and a clock signal are transmitted separately between a transmitter and receiver that use low-voltage differential signals (LVDS). In such a case, the configuration is such that the rise of the clock signal is always matched to a change in the data signal. There is therefore a requirement to generate a clock signal that ensures that the timings of the data signal and the clock signal match, particularly at the receiver.
A block diagram of an ordinary transmitter and receiver is shown in FIG. 10. A transmission clock signal and serial data that are transferred from a transmitter 71 to a receiver 72 are shown in FIG. 11. The serial data shown in FIG. 11 is data which is sent within one cycle of the transmission clock and which comprises 7 bits, by way of example. In other words, the serial data assumes a transmission rate that is seven times the frequency of the transmission clock, so that the transmission rate of the serial data will be 455 Mbps when the frequency of the transmission clock is 65 MHz.
The description first concerns the operation of the transmitter 71. The clock signal that is input to the transmitter 71 is increased sevenfold within a PLL block 77. Parallel data that is input to the transmitter 71 is converted into the serial data shown in FIG. 11 within a parallel/serial conversion block 79, based on this sevenfold sampling clock, then is sent to the receiver 72 as an LVDS signal from an LVDS output cell 73. The transmission clock shown in FIG. 11 is output from another LVDS output cell 74. This transmission clock has a frequency that is preferably one-seventh that of the sevenfold sampling clock, but the input clock signal could equally well be output unchanged.
The description now turns to the operation of the receiver 72. The clock signal that has been input to the receiver 72 is sent through an LVDS input cell 76 to a PLL block 78, where it is increased sevenfold. Serial data that has been input to the receiver 72 is sent through another LVDS input cell 75 to a serial/parallel conversion block 80, where it is converted into parallel data, based on the sevenfold sampling clock.
Instead of using PLL to generate the sampling clock, which has a frequency seven times that of the input clock, in the transmitter 71 and the receiver 72, seven-phase clock signals could be generated by PLL to have phases delayed by one-seventh the period of the input clock signal, then that seven-phase clock signals could be used as sampling clocks (refer to related applications such as Japanese Patent Application Laid-Open No. 9-74339).
To ensure synchronization between the clock signal and the data signal in the above described data transfer method, it is necessary to operate in such a manner that the rise of the clock signal that is an LVDS output always coincides with a change-point of the data signal. The rise in the clock signal must always be matched against the change-points in the data signal, even if there is a change in the period of the clock signal that is input to the transmitter 71.
A block diagram of the PLL circuit used for generating the clock signal in the receiver of FIG. 10, that is, a conventional clock generation circuit, is shown in FIG. 12. A voltage-controlled oscillator (VCO) 94 generates an output clock signal that oscillates at a frequency corresponding to a control voltage. The phase of the output clock signal generated by the VCO 94 is compared with the phase of the input clock signal in a phase comparator 91, and an error signal is generated in accordance with this phase difference. This error signal is integrated by a charge pump 92 and a low-pass filter (LPF) 93 and is applied to the VCO 94 as a control voltage.
Note that, in order to generate the seven-phase sampling clocks in the PLL circuit shown in FIG. 12, the VCO 94 is a ring oscillator which is configured of seven stages of differential buffers and the seven-phase sampling clocks can be obtained from the outputs of the differential buffers at each stage. The output of the final-stage differential buffer is fed back to the phase comparator 91.
To generate a clock signal that can reduce electro magnetic interface (EMI) noise, a method called a spread spectrum is used. With this method, the frequency of the clock signal is deliberately varied, to broaden the distribution of frequencies.
A chart showing the capability of the output clock signal to follow changes in the period of the input clock signal in the conventional clock generation circuit is shown in FIG. 13. The output clock signal of the clock generation circuit is unable to follow the period of the input clock signal directly, when it is varied in accordance with the spread spectrum between 15 ns and 14 ns, and changes slowly from 15 ns to 14.5 ns after a delay. During this time, the phase difference between the input clock signal and the output clock signal can reach 1.5 ns.
When the period of the input clock signal is 14 ns, the time width for one bit of data within the serial data used in the transfer is 2 ns. If the phase difference with respect to the output clock signal from the clock generation circuit is 1.5 ns during this time, the time margin between the serial data signal and the clock signal that is output from the clock generation circuit is reduced to no more than 0.5 ns.
Since it is necessary to ensure that the rise of the transmission clock always matches a change-point in the data during data transfer using LVDS, this large phase difference between the input clock signal and the output clock signal of the clock generation circuit causes a problem.
Phase difference, called jitter, can also occur in the input clock signal. This phase difference is on the order of 300 to 400 ps, but it causes a problem in that the output of the VCO cannot follow this jitter.
An objective of the present invention is to provide a clock generation circuit that generates multi-phase output clock signals which immediately follow any change in the period of an input clock signal, as well as a serial/parallel conversion device, a parallel/serial conversion device, and a semiconductor device using the same.
A clock generation circuit in accordance with one aspect of the present invention, which generates multi-phase output clock signals based on an input clock signal, comprises:
a voltage-controlled oscillator which oscillates an output signal having a frequency that varies in accordance with a control voltage;
a phase comparator which compares the phase of the input clock signal and the phase of the output signal of the voltage-controlled oscillator, to detect a phase difference therebetween;
a control voltage generation circuit which generates the control voltage in accordance with the phase difference detected by the phase comparator; and
a variable delay circuit which generates the multi-phase output clock signals by delaying the input clock signal in accordance with the control voltage.
With this aspect of the present invention, the multi-phase output clock signals are not output from the voltage-controlled oscillator, but they are output by a variable delay circuit having a delay determined by the same voltage as the control voltage applied to the voltage-controlled oscillator. This variable delay circuit delays the input clock signal by an amount determined by the control voltage, thus making it possible to generate multi-phase output clock signals that directly follow any change in the period of the input clock signal.
In this case, the voltage-controlled oscillator may comprise a plurality of differential buffer circuits connected in a ring shape. This variable delay circuit may comprise a plurality of differential buffer circuits having the same configuration as the plurality of differential buffer circuits that are comprised with the voltage-controlled oscillator. In addition, if the voltage-controlled oscillator has n of these differential buffer circuits, the variable delay circuit can have at least 2n of these differential buffer circuits. This configuration makes it possible to generate an n-phase output clock signal having phase differences (T/n) obtained by dividing one cycle (T) of the input clock signal into substantially n parts.
The multi-phase output clock signals may be generated on the basis of outputs from odd-numbered differential buffer circuits from among the at least 2n differential buffer circuits, or they may be generated on the basis of outputs from even-numbered differential buffer circuits from among the at least 2n differential buffer circuits.
The voltage-controlled oscillator and the variable delay circuit may be formed on the same semiconductor substrate. This makes it possible to cancel out any variations between the differential buffer circuits configuring the voltage-controlled oscillator and the variable delay circuit, increasing the capability of the device to follow changes in the period of the input clock signal.
Another aspect of the present invention relates to a serial/parallel conversion device and a parallel/serial conversion device both comprising the above described clock generation circuit. The use of multi-phase output clock signals as sampling clocks necessary for the conversion performed thereby makes it possible for the device to follow any change in the period of the input clock signal directly, thus matching the rise of the sampling clock to changes in the data.
A further aspect of the present invention relates to a semiconductor device wherein a voltage-controlled oscillator and a variable delay circuit used in a serial/parallel conversion device or a parallel/serial conversion device are formed on the same semiconductor substrate. This semiconductor device is capable of implementing highly accurate serial/parallel conversion or parallel/serial conversion.